FIG. 3 is a block diagram of a conventional information card comprising a plurality of integrated circuits including volatile memory circuits. In FIG. 3, reference numeral 3 designates a supply voltage detecting circuit for monitoring the voltage of an external 5 V power supply 7 supplied through a power supply input terminal 25. The supply voltage detecting circuit 3 has its first output terminal 4 connected to a base of a PNP transistor 6. Its output turns the transistor 6 ON or OFF and switches between the external 5 V power supply 7 and the internal power supply 19. In addition, a second output terminal 5 of the supply voltage detecting circuit 3 is connected to a "H" active enable input terminal 9 of an address decoder 8 and a "H" active control input terminal 15 of a buffer 14 for a card enable input. An output 11 of the address decoder 8 is connected to chip select input terminals 13.sub.1 to 13.sub.n of the plurality of volatile memory circuits 12.sub.1 to 12.sub.n, of the memory card. The volatile memory circuits 12.sub.1 to 12.sub.n are commonly connected to a power supply line on the collector side of the transistor 6 which switches between the external 5 V power supply 7 and the internal power supply 19. The power supply line is connected to a primary battery 18 through a diode 16 for preventing the flow of a reverse current and a current controlling resistor 17. Data stored in the volatile memory circuits 12.sub.1 to 12.sub.n is backed up by the primary battery 18. In addition, reference numeral 22 designates a resistor for pulling up an input of the buffer 14 for the card enable input to a voltage of the external power supply 7, reference numeral 21 designates a card enable terminal, reference numeral 24 designates a higher rank address input terminal for supplying a higher rank address input of the memory card to the address decoder 8, and reference numeral 26 designates a 0 V power supply input terminal. The supply voltage detecting circuit 3, the address decoder 8, the volatile memory circuits 12.sub.1 to 12.sub.n, the buffer 14 and the like can be an IC (integrated circuit).
Next, operation of this conventional example will be described in reference to an operating signal waveform of the supply voltage detecting circuit 3 shown in FIG. 2. In FIG. 3, when memory is backed up, that is, when a voltage of the external 5 V power supply 7 is less than, for example 4.25 V (FIG. 2(a)), it is detected by the supply voltage detecting circuit 3 and an output of the first output terminal 4, that is, an absorption current output is turned OFF (figure,) and a voltage output of the second output terminal 5 attains "L" level (FIG. 2(b)). Therefore, the transistor 6 is turned OFF and the "H" active enable input terminal 9 of the address decoder and the "H" active output control input terminal 15 of the buffer 14 for the card enable input the "L" level. Therefore, all of the outputs 11 of the address decoder 8 attain "H" level and all of the volatile memory circuits 12.sub.1 to 12.sub.n in the memory card attain a standby state with a supply voltage supplied from the internal power supply 19, that is, the primary battery 18, and data in the memory circuits 12.sub.1 to 12.sub.n is stored.
A description is given of a case where in the above memory backup state, there is an electrostatic discharge through the memory card body (more specifically, an electrostatic discharge generated when the memory card held by a person charged with electricity is inserted into equipment). If a discharge current or an induced current I [A] due to the discharge current flows into the "H" active enable input line 9a (which is the same as the "H" active output control input line of the card enable input buffer 14) of the address decoder 8 for t.sub.0 [sec], a voltage expressed by the following equation is generated on the "H" active enable input line 9a of the address decoder 8, that is; ##EQU1## where C.sub.0 line capacitance [F] between the enable input line 9a and the 0 V power supply 20. When a voltage V exceeds a threshold voltage of the "H" active enable input line 9a of the address decoder 8, an output signal 11 appears and one of the volatile memory circuits 12.sub.1 to 12.sub.n becomes active, which could cause the stored data in the memory circuits 12.sub.1 to 12.sub.n to be destroyed (erroneously overwritten).
Since the conventional memory card is structured as described above, the line capacitance between the enable input line of the address decoder and the 0 V power supply is small (several pF), so that the data stored in the memory card is sometimes destroyed by a comparatively small discharge current I. For example, when V=2 volts, C.sub.0 =5 pF, t.sub.0 =100 nsec, and ##EQU2## a discharge current I is as follows; ##EQU3## However, the address decoder erroneously operates at this current, causing the data stored in the memory card to be destroyed.